H.265帧内模式判决并行计算方法研究与实现
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摘要
针对H.265帧内编码算法编码速度慢的问题,基于现场可编程逻辑门阵列(FPGA)设计了一种并行帧内模式判决架构.首先通过理论推导,证明可以将多层次多尺度编码块的模式判决问题转化为单一层次多个小尺度编码块模式判决的叠加问题;其次,在编码块内部通过细粒度并行实现快速模式判决,在编码块之间通过窗口流水方式实现快速处理;最终在FPGA上设计并实现了该帧内快速模式判决架构.实验结果表明,本文算法最高可达到93.6x的加速比,且编码后的视频质量损失较小(PSNR平均降低0.71dB).
A parallel mode decision architecture based on Field-Programmable Gate Array( FPGA) is designed for the problem of slowcoding speed of H.265 intra frame coding algorithm.Firstly,problem of multi-scale mode decision is improved by dividing into the superposition problem of single-level small scale mode decision with theoretical derivation;secondly,fine-grained parallel implementation is used in single coding unit for fast mode decision while pipelined windowbuffer is being used to speed up processing time between coding units;Finally,the architecture was designed and implemented on FPGA.The experimental results showthat the speed up ratio of the design is up to 93.6 with a little quality drop( PSNR decreased 0.71 dB in average).
A parallel mode decision architecture based on Field-Programmable Gate Array( FPGA) is designed for the problem of slowcoding speed of H.265 intra frame coding algorithm.Firstly,problem of multi-scale mode decision is improved by dividing into the superposition problem of single-level small scale mode decision with theoretical derivation;secondly,fine-grained parallel implementation is used in single coding unit for fast mode decision while pipelined windowbuffer is being used to speed up processing time between coding units;Finally,the architecture was designed and implemented on FPGA.The experimental results showthat the speed up ratio of the design is up to 93.6 with a little quality drop( PSNR decreased 0.71 dB in average).
引文
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[2]Jiang Y,Llamocca D,Pattichis M,et al.A unified and pipelined hardware architecture for implementing intra prediction in HEVC[C].Southwest Symposium on Image Analysis and Interpretation(SSIAI),IEEE,2014:29-32.
[3]Abdelrasoul M,Sayed MS,Goulart V.Diagonal-based fast intramode decision algorithm for HEVC[J].IET Image Processing,2017,11(10):888-898.
[4]Zhang T,Sun MT,Zhao D,et al.Fast intra-mode and CU size decision for HEVC[J].IEEE Transactions on Circuits and Systems for Video Technology,2017,27(8):1714-1726.
[5]Zhang Jun,Dai Feng,Ma Yi-ke,et al.Multi-level and fine-grained parallel HEVC intra mode decision method[J].Journal of Computer Research and Development,2016,53(4):873-883.
[6]Zhang Jun,Dai Feng,Ma Yi-ke,et al.Highly parallel mode decision method for HEVC[C].Proc of the 30th Picture Coding Symp(PCS),Piscataway,NJ:IEEE,2013:281-284.
[7]Koivula A,Viitanen M,Vanne J,et al.Parallelization of Kvazaar HEVC intra encoder for multi-core processors[C].2015 IEEEWorkshop on Signal Processing Systems(SiPS),Hangzhou,2015:1-6.
[8]Maazouz M,Bahri N,Batel N,et al.Parallel implementation of Kvazaar HEVC on multicore ARMprocessor[C].2016 8th International Conference on Modelling,Identification and Control(IC-MIC),Algiers,2016:1086-1091.
[9]Atapattu S,Liyanage N,Menuka N,et al.Real time all intra HEVCHD encoder on FPGA[C].IEEE,International Conference on Application-Specific Systems,Architectures and Processors(ASAP),IEEE Computer Society,2016:191-195.
[10]Oezkan MA,Reiche O,Hannig F,et al.A highly efficient and comprehensive image processing library for C++-based high-level synthesis[C].International Workshop on FPGAs for Software Programmers(FSP),Ghent,Belgium,2017:1-10.
[11]Kalali E,Hamzaoglu I.FPGA implementation of HEVC intra prediction using high-level synthesis[C].IEEE,International Conference on Consumer Electronics-Berlin(ICCE-Berlin),IEEE,2016:163-166.
[12]Pastuszak G,Abramowski A.Algorithm and architecture design of the H.265/HEVC intra encoder[J].IEEE Transactions on Circuits and Systems for Video Technology,2016,26(1):210-222.
[5]张峻,代锋,马宜科,等.多层次细粒度并行HEVC帧内模式选择算法[J].计算机研究与发展,2016,53(4):873-883.