数字电路阈值故障测试生成算法（英文）
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摘要
提出一种有效的数字电路故障阈值故障测试生成算法。首先构造出数字电路的阈值测试模型,通过这个模型可以区分出可接受故障和不可接受故障,然后使用成熟的固定故障测试生成算法得到不可接受故障的测试生成矢量。在ISCAS’85和ISCAS’89电路上的实验结果表明:该算法的故障覆盖率能达到96%,故障测试生成时间少于0. 019 s。
An effective faults test generation algorithm based on threshold for digital circuits is proposed in this paper. Firstly,digital circuit's threshold test generation model is constructed,through which the acceptable fault and the unacceptable fault can be distinguished. Then the threshold test vectors can be obtained for unacceptable faults by using mature stuck-at faults test generation algorithm. The experimental results on the ISCAS'85 and ISCAS'89 circuits show that the fault coverage of the algorithm can reach up to 96% and the test generation time is less than 0. 1 second.
An effective faults test generation algorithm based on threshold for digital circuits is proposed in this paper. Firstly,digital circuit's threshold test generation model is constructed,through which the acceptable fault and the unacceptable fault can be distinguished. Then the threshold test vectors can be obtained for unacceptable faults by using mature stuck-at faults test generation algorithm. The experimental results on the ISCAS'85 and ISCAS'89 circuits show that the fault coverage of the algorithm can reach up to 96% and the test generation time is less than 0. 1 second.
引文
[1]JIANG Z,GUPTA S K.An ATPG for Threshold Testing:Obtaining Acceptable Yield in Future Processes[C]//Proc.ITC.2002(9):824-933.
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[5]JAVIER F,PETER M K.Search based algorithms for test sequence generation in functional Testing[J].Information and Software Technology,2014,7(14):4-10.
[6]STELIOS N,MARIA K M.Multiple detection test generation with diversified fault partitioning paths[J].Microprocessors and Microsystems,2014,38(4):85-90.
[7]HIDEYUKI I,KENTA S.A Practical Approach to Threshold Test generation for Error Tolerant Circuits[C]//2009 Asian Test Symposium.2009:171-176.
[8]WU Fan.Fault Diagnosis of Anolog Cirsuit based on Wavelet Neutral Network[J].Computer Measueement and Control,2014,22(11):3521-3523.
[9]SHIN D,GUPTA S K.A Re-Design for Datapath Modules in Error Tolerant Applications[C]//Proc ATS.2008:431-437.
[10]REZA N P,NAFISEH M.A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC[J].Microelectronics Journal,2013,35(1):48-50.
[11]WEI C R,YAN X L,SHANG Y L.Research and Implementation of Boundary Scan Test Generation and Fault Diagnosis[J].Computer Engineering,2015,41(1):303-306.
[2]CHUNG H,ORTEGA A.Analysis and Testing for Error Tolerant Motion Estimation[C]//Proc DFT.2005:514-522.
[3]HSIEH T Y,LEE K J,BREUER M A.Reduction of Detected Acceptable Faults for Yield Improvement via error-Tolerance[C]//Proc DATE.2007:1598-1599.
[4]SHAHIDI S,GUPTA S K.A theory of Error-Rate Testing[C]//Proc ICCD.2003:433-434.
[5]JAVIER F,PETER M K.Search based algorithms for test sequence generation in functional Testing[J].Information and Software Technology,2014,7(14):4-10.
[6]STELIOS N,MARIA K M.Multiple detection test generation with diversified fault partitioning paths[J].Microprocessors and Microsystems,2014,38(4):85-90.
[7]HIDEYUKI I,KENTA S.A Practical Approach to Threshold Test generation for Error Tolerant Circuits[C]//2009 Asian Test Symposium.2009:171-176.
[8]WU Fan.Fault Diagnosis of Anolog Cirsuit based on Wavelet Neutral Network[J].Computer Measueement and Control,2014,22(11):3521-3523.
[9]SHIN D,GUPTA S K.A Re-Design for Datapath Modules in Error Tolerant Applications[C]//Proc ATS.2008:431-437.
[10]REZA N P,NAFISEH M.A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC[J].Microelectronics Journal,2013,35(1):48-50.
[11]WEI C R,YAN X L,SHANG Y L.Research and Implementation of Boundary Scan Test Generation and Fault Diagnosis[J].Computer Engineering,2015,41(1):303-306.