Replacement fin processing for III-V on Si: From FinFets to nanowires

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• 作者：Niamh Waldron ; ^{niamh.waldron@imec.be" class="auth_mail" title="E-mail the corresponding author} ; Clement Merckling ; Lieve Teugels ; Patrick Ong ; Farid Sebaai ; Kathy Barla ; Nadine Collaert ; Voon-Yew (Aaron) Thean
• 关键词：III-V ; FinFet ; Gate-All-Around (GAA) ; Nanowire ; InGaAs ; MOS
• 刊名：Solid State Electronics
• 出版年：2016
• 出版时间：January 2016
• 年：2016
• 卷：115
• 期：part_PB
• 页码：81-91
• 全文大小：3467 K

文摘

In this paper we review the details and results of the replacement fin process technique used to successfully demonstrate InGaAs based channel devices from FinFets to ultra scaled nanowires on 300 mm Si substrates. For FinFet devices a Mg p-type doping solution was developed to counteract the unintentional n-type doping of the InP buffer layer which resulted in high source-drain leakage. However, the performance of these devices is found to be limited by the Mg doping as the mobility is degraded. By switching to a GAA architecture the problem of source-leakage through the InP buffer is effectively eliminated and best devices with L_G = 60 nm have a peak transconductance of 1030 μS/μm with a SS_SAT of 125 mV/dec are achieved. A comparison of gate first to gate last processing highlights the importance of using a low thermal budget process to maintain the integrity of the InGaAs/high-allcaps">k interface. Nanowires with a diameter of 6 nm were demonstrated to show quantization induced immunity to D_it resulting in a SS_SAT as low as 66 mV/dec for 85 nm L_G devices.