Underlapped FinFET on insulator: Quasi3D analytical model

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• 作者：Vandana Kumari^a ; ^{vandanakumari511@gmail.com} ; K. Sharmetha^b ; ^{sharmetha208@gmail.com} ; Manoj Saxena^c ; ^{saxena_manoj77@yahoo.co.in} ; Mridula Gupta^d ; ^{mridula@south.du.ac.in}
• 关键词：FinFET ; ATLAS ; Underlap ; 3D modeling
• 刊名：Solid-State Electronics
• 出版年：2017
• 出版时间：March 2017
• 年：2017
• 卷：129
• 期：Complete
• 页码：138-149
• 全文大小：1689 K
• 卷排序：129

文摘

Sub-threshold drain current model for underlap FinFET. Impact underlap region on the analog and RF performance has been investigated. Higher underlap length shows poor device characteristics. Superposition technique is used to evaluate channel potential.