文摘
The traditional memory hierarchy design can smooth the data stream and instruction stream. However, the bandwidth of the instruction stream and data stream are still the main challenge for high-performance microprocessor systems. To improve the data and instruction fetchers, the proposed buffering architecture can exploits both the temporal and spatial localities with a relation-exchanging buffering mechanism. On buffers hit, the dynamic sequences of instruction or data can be reused. At the same time, the prefetching mechanism will be enabled to prefetch the instruction/data being used in the near future. According to the simulation results, the proposed buffering mechanism with the depth 3 and 64-byte line size, which only needs extra 4 % hardware cost, is a cost-ineffectiveness choice. The hit rate of an ABP buffer can 22 % outperforms that of loop buffer architecture to fetch instruction stream and 7 % outperform that of FIFO strategy to fetch data stream.
