Heterogeneous 3-D circuits: Integrating free-space optics with CMOS

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• 作者：Ioannis Savidis^a ; ^{isavidis@coe.drexel.edu" class="auth_mail" title="E-mail the corresponding author} ; ^{ioannis.savidis@drexel.edu" class="auth_mail" title="E-mail the corresponding author} ; ; Berkehan Ciftcioglu^b ; Jie Xu^b ; Jianyun Hu^b ; Manish Jain^b ; Rebecca Berman^b ; Jing Xue^b ; Peng Liu^b ; Duncan Moore^b ; ^{moore@optics.rochester.edu" class="auth_mail" title="E-mail the corresponding author} ; Gary Wicks^b ; ^{wicks@optics.rochester.edu" class="auth_mail" title="E-mail the corresponding author} ; Michael Huang^c ; ^{mihuang@ece.rochester.edu" class="auth_mail" title="E-mail the corresponding author} ; Hui Wu^c ; ^{hwu@ece.rochester.edu" class="auth_mail" title="E-mail the corresponding author} ; Eby G. Friedman^c ; ^{friedman@ece.rochester.edu" class="auth_mail" title="E-mail the corresponding author}
• 关键词：3-D IC ; Free-space optical networks ; Optical interconnects ; Heterogeneous 3-D ICs
• 刊名：Microelectronics Journal
• 出版年：2016
• 出版时间：April 2016
• 年：2016
• 卷：50
• 期：Complete
• 页码：66-75
• 全文大小：4064 K

文摘

A three-dimensional (3-D) integrated circuit combining free-space optical interconnects (FSOI) with CMOS devices has been developed. An overview of the combined optical and CMOS system is described. Experimental data and simulated results are provided. A 3-D integrated test circuit merging the free-space optical network with gallium arsenide based vertical cavity surface emitting lasers (VCSELs) and germanium based photodetectors has been experimentally tested. The prototype 3-D IC test circuit exhibits a 3.3 GHz bandwidth and a 5.1 mW total power consumption per link. The bandwidth is limited due to the use of 5 GHz bandwidth commercial VCSELs and the large inductive impedance of the wirebonds attaching the VCSELs and photodetectors to the I/O pads. The design of transmitter circuits for the 3-D integrated free-space optical interconnect system is discussed, and simulated extrapolated results on operating frequency and bandwidth are provided. The microprocessor operates at 333 MHz and includes a bus width of 64 bits, requiring a FSOI bandwidth of 10.65 Gbps after serialization.