Identifying the trap configuration is essential for understanding non-volatile memory device performance and reliability. In this paper, an accurate approach to determine the trap distribution in the charged layer is presented. The analysis is done by Trap Spectroscopy by Charge Injection and Sensing (TSCIS) technique [1] varying charge injection time and gate voltage independently. Varying time determines the physical charge injection distance. The conversion of time into distance is done based on theoretical modeling simplified to only electron capturing from Shockley–Read–Hall (SRH) statistics. Direct tunneling of the electrons from quantized energy levels in inverted Si channels to the oxide traps is considered with a WKB approximation. This approach gives the electron scanning rate in SiO
2 as 0.19 nm/decade, which is consistent with previous noise/direct tunneling analyses.
The effect of the residual charge on the potential energy barrier for the electron tunneling is also accounted for in the electron scanning distance calculation by including Gauss’ law. Considering the charge voltage determines the trap energy level, and we can finally obtain the trap distribution ‘map’ inside the oxide. This TSCIS technique is applied to profile the oxide trap density in oxide stacks for flash memory application successfully. Traps located spatially as far as 3 nm from the Si/SiO2 interface can be probed with 1000 s of charge injection time in case of a 0.87 nm SiO2/10 nm Al2O3 stack.
