Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications

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• 作者：Achinta Baidya^a ; ^{achintabaidya@yahoo.com} ; Trupti Ranjan Lenka^b ; Srimanta Baishya^b
• 关键词：Junctionless transistor ; Inverter ; Mixed mode simulation ; High-K ; Universal gates
• 刊名：Superlattices and Microstructures
• 出版年：2016
• 出版时间：December 2016
• 年：2016
• 卷：100
• 期：Complete
• 页码：14-23
• 全文大小：1809 K
• 卷排序：100

文摘

Circuit performance of ultra-thin 3D double gate JNT using mixed mode simulations. An extensive analysis of JNT made inverter circuit and universal logic gates characteristics. Improvment of JNT based circuit performance and exploration of the influence of high-K gate dielectrics. Use of high-K dielectric based gate oxide improves the circuit performance of JNT. Investigation with fixed CL for uniform comparison and varied CL in inverter for understanding of CL effect.