Process modules for GeSn nanoelectronics with high Sn-contents

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• 作者：C. Schulte-Braucks^a ; ^{c.schulte-Braucks@fz-juelich.de} ; S. Glass^a ; E. Hofmann^a ; D. Stange^a ; N. von den Driesch^a ; J.M. Hartmann^b ; ^c ; Z. Ikonic^d ; Q.T. Zhao^a ; D. Buca^a ; S. Mantl^a
• 关键词：GeSn ; MOSFET ; High-k/metal gate ; NiGeSn
• 刊名：Solid-State Electronics
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：128
• 期：Complete
• 页码：54-59
• 全文大小：2184 K
• 卷排序：128

文摘

This paper systematically studies GeSn n-FETs, from individual process modules to a complete device. High-k gate stacks and NiGeSn metallic contacts for source and drain are characterized in independent experiments. To study both direct and indirect bandgap semiconductors, a range of 0–14.5 at.% Sn-content GeSn alloys are investigated. Special emphasis is placed on capacitance-voltage (C-V) characteristics and Schottky-barrier optimization. GeSn n-FET devices are presented including temperature dependent I-V characteristics. Finally, as an important step towards implementing GeSn in tunnel-FETs, negative differential resistance in Ge0.87Sn0.13 tunnel-diodes is demonstrated at cryogenic temperatures. The present work provides a base for further optimization of GeSn FETs and novel tunnel FET devices.