As transistors scale, system temperatures are rising, and with them, cooling costs. Faced with such challenges, designers have developed a variety of techniques to reduce temperatures at design-time, through floorplanning, and at run-time, using dynamic thermal management. Multi-core floorplanning, in particular, presents unique opportunities for temperature management: for example, cores can be individually floorplanned to reduce system temperature, and L2 cache banks can be interleaved between cores to separate hot components and take advantage of spatial thermal filtering.
In this paper, we present an evaluation of the potential thermal benefits of multi-core floorplanning. We evaluate techniques from the literature, including manipulating core orientation, L2 cache bank insertion, and hierarchical floorplanning, and introduce two new techniques, core mingling and core scattering, in order to bound the potential benefits of temperature-aware floorplanning. For multi-core architectures up to 16 cores, we observe that simply inserting L2 cache banks between identically floorplanned and oriented cores captures 82 % of the possible temperature reduction available to multi-core floorplanning. For many-core architectures, L2 cache insertion continues to have the most significant effect on temperature. This is good news for designers: while in principle, developing different floorplans for each instance of a core may further reduce temperatures, such techniques require substantial floorplanning effort and introduce new validation requirements and are not in fact necessary.
