刊名:Analog Integrated Circuits and Signal Processing
出版年:2017
出版时间:January 2017
年:2017
卷:90
期:1
页码:263-272
全文大小:
刊物类别:Engineering
刊物主题:Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing;
出版者:Springer US
ISSN:1573-1979
卷排序:90
文摘
A high speed high resolution direct digital frequency synthesizer (DDFS) architecture is presented. The proposed architecture combines the advantage of ROM-based DDFS and nonlinear DAC (NLDAC) based DDFS. The phase-to-amplitude mapping is implemented with NLDAC coarse quantization and further increase its resolution by adding a ROM-based piecewise linear interpolation. ROM size is reduced by using coarse-fine decomposition. A ROM compression ratio of 32 is achieved by further combing the adjacent lines in the same segment into one straight line. A 4-GHz 32-bit DDFS is implemented based on the proposed architecture. The prototype DDFS is fabricated in 0.25 μm SiGe HBT process. The DDFS with 9-bit amplitude resolution are capable of producing a minimum spurious-free dynamic range (SFDR) of 46 dBc up to Nyquist frequency at the clock frequency of 4.0 GHz. Compared with state-of-the-art DDFSs the proposed DDFS demonstrates excellent performance.
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