Fast Implementation of Different LTE Physical Downlink Control Channels Using FPGA

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• 作者：M. A. Mohamed ; H. M. Abdel-Atty…
• 关键词：Long term evolution (LTE) ; Physical downlink control channel (PDCCH) ; Downlink control information (DCI) ; Multiple input multiple output (MIMO) ; Field programmable gate array (FPGA) ; Register transfer level (RTL)
• 刊名：Wireless Personal Communications
• 出版年：2015
• 出版时间：December 2015
• 年：2015
• 卷：85
• 期：3
• 页码：1525-1559
• 全文大小：5,670 KB
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• 作者单位：M. A. Mohamed (1)
  H. M. Abdel-Atty (2)
  Mohy El-Din A. Abou-El-Seoud (1)
  W. M. Raslan (3)
  
  1. Electronics and Communications Engineering Department, Faculty of Engineering, Mansoura University, Mansoura, Egypt
  2. Electronics and Communications Engineering Department, Faculty of Engineering, PortSaed University, Port Said, Egypt
  3. Electronics and Communications Engineering Department, Faculty of Engineering, Sinai University, Arish, Egypt
  
• 刊物类别：Engineering
• 刊物主题：Electronic and Computer Engineering
  Signal,Image and Speech Processing
  Processor Architectures
  
• 出版者：Springer Netherlands
• ISSN：1572-834X

文摘

Hardware implementation of LTE-advanced systems using FPGA technology is a highly promising technology for mobile communications and wireless networks researchers. The objective of this paper is to improve the processing speed; the system capabilities; the power consumption, and the processing delay of LTE-advanced downlink control channels due to the parallel processing nature of FPGA. Basically, the physical downlink control channel (PDCCH) is used to carry downlink control information (DCI). In which, an optimized HDL design for both transmitter and receiver of PDCCH will be presented. The design process of PDCCH transmitter and receiver are carried out in architecture under different antenna configurations including: single input single output: 1 × 1; multiple input multiple output (MIMO) 2 × 2, and MIMO 4 × 4. The complete LTE-advanced physical layer has been coded using VHDL as one of the most famous HDL languages. Designs have been synthesized using Xilinx Integrated Software Environment tool 14.2 on Xilinx Virtex-5 XC5VLX220T_FF1738 as well as Xilinx Spartan-6 XC6SLX45_2CSG324, the performance indices of these two FPGA kits, will be compared. To simulate the system on ModelSim SE 6.5, based on synthesize and implementation, in terms of register transfer level design, FPGA editor, and Xilinx Power Analyzer are discussed into an FPGA kit from the Xilinx vendor. As a result of the system implementation process, it was found that speed; number of registers and power consumption are improved. Finally, it is clear that the hardware is much faster than the software, as well as, reducing the power dissipation in Spartan-6 with respect to Vitex-5 FPGA configurations.