Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor

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• 作者：Avikal Bansal (1)
  M. Jagadesh Kumar (1)
  
• 关键词：2D numerical simulation ; Laterally double diffused metal oxide semiconductor field effect transistor (LDMOSFET) ; ON ; resistance ; Parasitic BJT ; Power MOSFET ; Silicon on insulator (SOI)
• 刊名：Journal of Computational Electronics
• 出版年：2014
• 出版时间：December 2014
• 年：2014
• 卷：13
• 期：4
• 页码：857-861
• 全文大小：331 KB
• 参考文献：1. Kumar, M.J., Sithanandam, R.: Extended-p \(^{+}\) stepped gate LDMOS for improved performance. IEEE Trans. Electron Devices 57(7), 1719-724 (Jul. 2010)
  2. Goyal, N., Saxena, R.S.: A new LDMOSFET with tunneling junction for improved on-state performance. IEEE Electron Device Lett. 34(1), 90-2 (Jan. 2013)
  3. Sithanandam, R., Kumar, M.J.: Linearity and speed optimization in SOI LDMOS using gate engineering. Semicond. Sci. Technol. 25(1), 015006 (Jan. 2010)
  4. Kumar, M.J., Bansal, A.: Improving the breakdown voltage, on-resistance and gate-charge of InGaAs LDMOS power transistors. Semicond. Sci. Technol. 27(10), 105030 (Oct. 2012)
  5. Kong, M., Du, W., Chen, X.: Study on dual channel n-p-LDMOS power devices with three terminals. IEEE Trans. Electron Devices 60(10), 3508-514 (Oct. 2013)
  6. Verma, V., Kumar, M.J.: Study of the extended \(\text{ p }+\) dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFET’s. IEEE Trans. Electron Devices 47(8), 1678-680 (Aug. 2000)
  7. Atlas User’s Manual: Device Simulation Software. Silvaco Inc., Santa Clara, CA (May 2011)
  
• 作者单位：Avikal Bansal (1)
  M. Jagadesh Kumar (1)
  
  1. Department of Electrical Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi?, 110 016, India
  
• ISSN：1572-8137

文摘

We present a new parasitic bipolar junction transistor (BJT) enhanced silicon on insulator (SOI) laterally double diffused metal oxide semiconductor (LDMOS), called BJT enhanced LDMOS (BE-LDMOS). The proposed device utilizes the parasitic BJT present in an LDMOS to increase the drain current for a given gate voltage, resulting in a reduction in the ON-resistance by 26.2?% and improving the switching speed by 7.8?% for BE-LDMOS as compared to the comparable LDMOS. These improvements are without degradation in other performance parameters such as off state breakdown voltage and transconductance. The process steps for fabricating BE-LDMOS are same as that for LDMOS except for an additional metal contact.