摘要
本文设计了一种软硬件结合的简化方案,通过合理设计硬件、设计SYSREF信号的扇出控制逻辑,在一定采样率范围内满足JESD204B协议ADC多片多通道之间采样点相对时延固定,从而确保各通道采集信号相位一致。JESD204B协议支持的确定性延迟特性保证了设计实现。验证方案的测试电路采用XilinxK7系列FPGA控制两片AD9694(采样率320Msps)同步采集,证实设计方案满足应用需求。
引文
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