Design of Image Signal Processor for Hardware Size

详细信息    查看全文 | 推荐本文 |

英文篇名：Design of Image Signal Processor for Hardware Size 作者：Junghwan ; PARK ; Jong-sik ; PARK ; Jaekyung ; WEE ; Boo-gyoun ; KIM ; Seok ; LEE ; Seong-soo ; LEE 英文作者：Junghwan PARK1,Jong-sik PARK1,Jaekyung WEE1,Boo-gyoun KIM1,Seok LEE2,Seong-soo LEE1(1.School of Electronics Engineering,Soongsil University,Seoul 156-743,Korea;2.Intelligent System Research Division,Korea Institute of Science and Technology,Seoul,Korea) 英文关键词：Image Signal Processing;vision camera;low area;image process 中文刊名：CSKX 英文刊名：测试科学与仪器(英文版) 机构：School of Electronics Engineering,Soongsil University;Intelligent System Research Division,Korea Institute of Science and Technology; 出版日期：2010-12-15 出版单位：Journal of Measurement Science and Instrumentation 年：2010 期：v.1;No.4 基金：sponsored by ETRI System Semiconductor Industry Promotion Center,Human Resource Development Project for SoC Convergence and“System IC2010”project of Korea Ministry of Knowledge Economy 语种：英文; 页：CSKX201004021 页数：4 CN：04 ISSN：14-1357/TH 分类号：89-92

摘要

The Image sensor needs various image processing by Image Signal Processor(ISP)to improve image quality.Conventional cameras have their own software ISP functions to perform in PC instead of using commercial ISP chips.However these methods have problems such as large computation for image processing.In this paper,th authors proposed ISP that significantly reduced chip area by efficiently sharing of hardware and software.Large operation blocks are designed to hardware for high performances,and hardware is imployed simultaneously with software considering the size of the hardware.The implemented ISP can process Video Graphics Array(VGA)(640480)images and has 91 450 gates size in 0.35 μm process.
        The Image sensor needs various image processing by Image Signal Processor(ISP)to improve image quality.Conventional cameras have their own software ISP functions to perform in PC instead of using commercial ISP chips.However these methods have problems such as large computation for image processing.In this paper,th authors proposed ISP that significantly reduced chip area by efficiently sharing of hardware and software.Large operation blocks are designed to hardware for high performances,and hardware is imployed simultaneously with software considering the size of the hardware.The implemented ISP can process Video Graphics Array(VGA)(640480)images and has 91 450 gates size in 0.35 μm process.

引文

[1]Kimo Kim,In-Cheol Park,2006.Combined Image Signal Pro-cessing for CMOS Image Sensors.ISCAS.
    [2]Seung-Il Sonh,Dong-Hoon LEE,2007.Animplementation of ISPfor CMOSimagesensor.Journal of the KoreanInstitute of Maritime Information and Communication Sciences,11(3):555-562.
    [3]B.K.Gunturk,J.Glotzbach,Y.Altrnbasak,2005.Demosa-icking:color filter array interpolation.IEEE Signal Processing Magazine,21(1):44-54.
    [4]Kim,H.,et al,1998.Digital signal processor with efficient RGBinterpolation and histogramaccumulation.IEEE Trans-actions on Consumer Electronics,44:1389-1395.
    [5]Dillon,P.L.Pet al,1978.Colorimagingsystemusing asingle CCD area array.IEEE Journal of Solid-State Circuits,,13(2):28-33.
    [6]Won-woo Jang,Sung-mok Lee,Joo-young Ha,et al,2007.Comparison among Gamma(γ)Line Systems for non-linear gamma curve.Journal of the KoreanInstitute of Maritime In-formation and Communication Sciences,11(2):265-272.
    [7]C.Poynton,1993.Gamma and its disguises:the nonlinear mappings of intensity in perception,CRTs,fil mand video.SMPTEJ.,102(12):1099-1108.
    [8]Hopil Ahn,Hyowon Jeong,Jooyoung Ha,Kangjoo Kim,Bongsoon Kang,2009.Improvement Structure of RGB to YCbCr Conversion Block of ISP Platformin Mobile Phones.SoCconference,p.448-451.