摘要
在过去二十年中，为了满足人们日益增长的对多媒体的需求，媒体处理器得到了飞速发展，出现了各种各样的媒体处理器。根据其体系结构，媒体处理器可以分为专用可编程处理器、通用可编程处理器、专用处理器和可重配置处理器几大类。各类处理器都针对多媒体处理进行了扩展，增强其多媒体处理能力。通用可编程处理器中的精简指令集处理器(RISC)和专用可编程处理器中的数据信号处理器(DSP)各自具有不同的指令集结构和微结构特点，适合于不同的应用领域，出现了一系列RISC和DSP融合体的RISC／DSP架构，由于既善于执行系统程序，又善于执行信号处理程序，所以能够较好的适应复杂多媒体系统的要求。
本文介绍由浙江大学信息与电子工程学系SOC R&D小组开发的具有自主知识产权的，媒体数字信号处理器——MediaDSP3200(简称MD32)系列的设计和验证流程。MD32将RISC与DSP处理器的指令操作、寻址模式等要素充分融合，设计了并行操作、多媒体分裂模式等指令操作，形成了融合RISC、DSP、SIMD特点的一种新的指令集结构，并在此基础上设计了具有自身特色的RISC／DSP微结构组成和统一的流水划分结构，使得RISC／DSP体系既能够发挥RISC处理器的系统执行能力，又具有DSP处理器的数据处理能力，既有精简指令的优势，又有较强的算术运算能力，从而使MD32处理器更适合多媒体信息处理的需要。
为了对MD32进行快速验证，本文详细介绍了基于FPGA的媒体处理器通用软硬件协同仿真验证平台MPSP的设计。这一平台采用FPGA作为硬件仿真子平台，采用运行于上位机上的控制和驱动软件作为软件仿真子平台。软件和硬件子平台都可以快速的进行重配置，以适应不同的媒体处理器和不同的仿真要求。MPSP平台提供了一个可配置的IP库和一个包含大量API接口的软件库，基于这些库，协同仿真环境的设计过程被大大加速了。采用这一平台，我们对MD32进行了快速仿真验证。
为了对芯片进行测试，在芯片的测试过程中就必须考虑可测试性设计，在芯片中增加测试结构如扫描链等。媒体处理器的复杂度要求在其中采用多种测试结构。同时，完整的媒体处理器的集成开发环境包括嵌入式硬件调试环境，还需要在处理器中设计嵌入式调试接口。为此，本文介绍了基于JTAG的嵌入式调试接口的设计，即实现了芯片的结构测试和功能测试，也实现了硬件调试功能。基于这一接口，可以对媒体处理器进行边界扫描测试，也可以进行硬件单步、断点、观察处理器状态等等复杂的硬件调试。
Media processor is developed rapidly in the last twenty years to meet the fast increasing demand of multimedia application. Media processor can be classified into special purpose programmable processor, general purpose programmable processor, dedicated processor and reconfigurable processor. These processors have improved the compute power to meet the media processing requirement. Reduced Instruction Set Computer (RISC) and Digital Signal Processor (DSP) have different application areas due to their different Instruction Set Architecture (ISA) and micro-architecture. RISC/DSP is a hybrid of traditional RISC and DSP processor. Merit to both characteristics of RISC and DSP, RISC/DSP is more capable for complex media processing.
This paper describe a RISC/DSP processor-MediaDSP3200 serials, which is
developed by the Department of Information Science and Electronic Engineering in Zhejiang University. MD32 ISA is a novel architecture, which features with both RISC and DSP. Single Instruction Multi Data (SIMD) is also supported in MD32. A characterized RISC/DSP micro-architecture and unified pipeline is designed based on MD32 ISA. It is not only good at executing system tasks like RISC processor, but also expert in digital signal processing like DSP. This makes MD32 more powerful in multi-media signal processing.
To verify the design of MD32 quickly, FPGA based media processor hardware/software co-simulation platform is developed. This platform includes a FPGA based hardware sub-platform and a software sub-platform running on host PC. Both the hardware and the software can be re-configured quickly to accommodate different media processor for different simulation specification. The design of co-simulation environment on MPSP is based on library. A reconfigurable IP library and a software pack with API interfaces are provided as a part of MPSP. Based on this platform, the FPGA based co-simulation processing is greatly accelerated. MD32 is simulated on this platform and the design is verified.
To test the chip, DFT(design for testability) structure should be considered on the design. Test structures such as scan chain should be added to the processor. And ICE(in circuit emulator) is a indispensable component in the intergrated development environment of mdia processor. It requires an embedded debug interface. So an embedded debug interface based on JTAG is described on this paper. Based on this interface, both the structure and function test and the hardware debug such as single step,breakpoint and watch can be applied to MD32.
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