摘要
本文研究了基于NiosⅡ的FPGA-CPU调试技术。论文研究了NiosⅡ嵌入式软核处理器的特性；实现了以NiosⅡ嵌入式处理器为核心的FPGA-CPU调试系统的软、硬件设计；对两种不同类型的FPGA-CPU进行了实际调试，对实验数据进行了分析。
在硬件方面，为了控制和检测FPGA-CPU，设计并实现了FPGA-CPU的控制电路、FPGA-CPU的内部通用寄存器组扫描电路、存储器电路等；完成了各种外围设备接口的设计；实现了调试系统的整体设计。
在软件方面，设计了调试监控软件，完成了对FPGA-CPU运行的控制和信号状态的监测。这些信号包括地址和数据总线以及各种寄存器的数据等；实现了多种模式下的FPGA-CPU调试支持单时钟调试、单步调试和软件断点多种调试模式。此外，设计了专用的编译软件，实现了基于不同指令系统的伪汇编程序编译，提高了调试效率。
本文在实现了FPGA-CPU调试系统基础上，对两种指令系统不同、结构迥异的FPGA-CPU进行实际调试。调试结果表明，这种基于IP核的可复用设计技术，能够在一个FPGA芯片内实现调试系统和FPGA-CPU的无缝连接，能够有效地调试FPGA-CPU。
In this paper, the technology of FPGA-CPU debugging is discussed based on Nios II embedded processor. The characteristics of Nios II embedded processor is studied. The hardware and software design of the FPGA-CPU debugging system are accomplished. Two different types of FPGA-CPU are debugged with the debug system developed . The testing datum are analyzed.
As for hardware design, in order to control and monitor FPGA-CPU, several circuits are designed, which are the dual-port memory circuit, control circuit and scanning circuit etc. Besides, all inferface circuits between debuging system and FPGA-CPU are achieved
As for software design, the debuging software based on Nios II processor is completed, which can operate the dual-port memory, loading and controling testing programms. The software can monitor the FPGA-CPU running state. All information inside the FPGA-CPU can be obtainded , including registers , data bus and address bus etc. Several debuging mode are accomplished. They are single clock debugging model, one-step instruction debugging model, and breakpoint debugging model. These modes can be used alone or alternately.
In order to increase the efficiency of the debuging system, a compiler software has been completed, with which the assembler programmers can be compiled into their machine language.
On the implementation of debugging system, two types of FPGA-CPU are tested, whose instruction system and architecture are widely different. The debuging result demonstrates that the technology of debugging based on IP reuse can debug FPGA-CPU efficiently. The debuging system and the FPGA-CPU can be in one chip, achieving the seamless linking between the these parts.
引文
[1] Alfred L. Crouch. Design-For-Test For Digital IC's and Embedded Core Systems. 影印版．北京．中国电力出版社. 2004.1
[2] Rochit Rajsuman. System-on-a-Chip: Design and Test. USA: Advantest America R&D Center, Inc. 2000.
[3] Como, E Sonza Reorda, M. SquilleroGViolante, M. On the test of microprocessor IP cores. Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings. On page(s): 209-213
[4] 任爱锋，初秀琴，常存，孙肖子．基于FPGA的嵌入式系统设计．西安．电子科技大学出版社．2005．2
[5] 潘松，黄继业．SOPC技术实用教程．北京．清华大学出版社．2005．3
[6] David A．Patterson，John L．Hennessy．郑纬民等译．计算机组成与设计：硬件/软件接口(原书第三版)．北京．机械工业出版社．2007．4
[7] David A．Patterson，John L．Hennessy．郑纬民等译．计算机组成与设计：硬件/软件接口(原书第二版)．北京．清华大学出版社．2003．12
[8] Richard Bamett，Larry O'Cull．薛晓东，秦新建译．嵌入式C语言编程与Microchip PIC．北京．清华大学出版社．2005．7
[9] Randal E．Bryant，David O'Hallaron．龚奕利，雷迎春译．深入理解计算机系统．北京．中国电力出版社．2004．5
[10] William Stallings. Computer Organiztion and Architecture Designing for Performance. 北京电子工业出版社. 2001.
[11] William Stallings. Computer Organiztion and Architecture Designing for Performance. 北京 电子出版社，2001.
[12] 曾繁泰，陈美金．VHDL 程序设计．清华大学出版社， 2001．
[13] Rochit Rajsuman. System-on-a-Chip: Design and Test. USA: Advantest America R&D Center,Inc. 2000.
[14] Bricaud, P.J. IP Rreuse Creation for System-on-a-Chip Design. Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999. On page(s): 395—401. May 1999.
[15] Altera Corporation. Nios Ⅱ Hardware Development Tutorial. http://www.altera.com. 2005.
[16] Altera Corporation. Nios Ⅱ Software Developer's Handbook. http://www.altera.com. 2004.
[17] Altera Corporation. Designing with Nios Ⅱ and SOPC Builder. http://www.altera.com. 2005.
[18] Altera Corporation. Nios Ⅱ Flash Programmer User Guide. http://www.altera.com. 2005.
[19] Altera Corporation. Simulating Nios Embedded Processor Designs. http://www.altera.com.2003.
[20] Altera Corporation. Implementing Interrupt Service Routines in Nios Systems. http://www.altera.com. 2003.
[21] Altera Corporation. Avalon Bus Specification Reference Manual. http://www.altera.com. 2003.
[22] EDA先锋工作室，吴继华，王诚．Altera FPGA/CPLD设计(高级篇)．北京．人民邮电出版社．2005．
[23] EDA先锋工作室，王诚，吴继华等．Altera FPGA-CPLD设计(基础篇)．北京．人民邮电出版社．2005．
[24] Westor Wang．FPGA设计指导性原则．http://www.edaen.net & http://www.edacn.com.
