摘要
随着集成电路设计工艺水平的不断提高,高性能、低成本已成为SOC芯片设计的主要挑战,作为片上时钟发生器锁相环的设计变得非常关键。电荷泵锁相环具有易于集成、低功耗、低抖动、频率牵引范围大和静态相位误差小等优点,成为了当前数字锁相环产品的主流。
本文设计了一款面向16位定点DSP芯片的三阶电荷泵锁相环。文章在深入分析电荷泵锁相环设计理论的基础上,根据DSP芯片对锁相环的具体应用要求,确定了锁相环的总体电路结构和各项性能参数。然后将各项参数指标分到各个模块上,进行单元电路的设计。在单元电路的设计时,论文重点讨论并解决了下述问题:
1)鉴频鉴相器的优化设计,在降低死区的同时,有效地增加鉴相带宽;
2)采用开关在源极的新型电荷泵结构,在消除电荷共享效应的同时,具有开关加速的功能以及很高的电流匹配精度;
3)使用二阶无源RC环路滤波器降低了输出纹波,并对滤波器参数进行了优化设计;
4)压控振荡器采用四级延迟单元的环形振荡器,每级采用RS触发结构来产生差分输出信号,在有效降低静态功耗的同时,具有较好的抗噪声能力;
5)采用全定制设计的可编程分频器,在尽可能的减少设计单元的同时,实现对输出不同频率的调节要求。
所设计的电荷泵锁相环采用SMIC 0.35μm CMOS工艺实现,5V电源供电,其面积为502μm×496μm。仿真结果表明,锁相环的频率捕获范围为2MHz～60MHz,在VCO输出频率为20MHz时,环路的锁定时间为12.7μs,抖动的峰峰值小于512ps,功耗为6.2mW,能完全满足DSP芯片时钟系统的要求。
最后,为了DSP系统仿真的需要,论文还对所设计的电荷泵锁相环建立了Verilog功能模型,并对今后下一步工作中建立锁相环IP核,实现锁相环的可复用性作了展望。
With the rapid development of IC design and process, high performance and low cost are now the main challenges for SOC design. Phase-locked loop(PLL) used as clock generator on chip becomes very critical. Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL(Charge-pump PLL) has become one of the major digital PLL product.
This paper presents a third-order CPPLL used in the 16-bit fixed-point DSP. Based on the analysis of the theory of CPPLL and application requirements in the DSP, the structure and the performance specifications of the PLL are defined, and then the subcircuits are designed. During these procedures, this thesis discusses and solves the following problems:
1) Optimizes the PFD(Phase and Frequency Detector) to reduce the Dead-zone and increase the bandwidth of phase detector;
2) Adopts a new type of CP(Charge-Pump) with accelerated switch in source, it solve the effect of charge sharing and with high current matching accuracy;
3) Adopts a second-order RC filter to reduce the output ripple, and optimizes the parameters of the filter;
4) Adopts a ring VCO which consists of four stage of delay elements, each of them adopts the RS flip-flop to generate difference output. This structure reduces the power dissipation effectively and with much better performance in anti-noise;
5) Design the programmable frequency divider by method of full custom. It reduces elements as much as possible and meets the different requirements in the frequency of output clock.
The CPPLL is completed in SMIC 0.35um CMOS process with 5V supply voltage, the area of the chip is 502μm×476μm. Simulation results show that the PLL can operate from 2MHz to 60MHz. When the output of VCO is 20MHz, the lock time of the PLL is 12.7μs, the peak-to-peak jitter is less than 512ps, and its power dissipation is only 6.2mW, so it can fully saitisfy the requirements of the DSP clock system.
At the end, this thesis creates the Verilog function model of the CPPLL in order to meet the demand of DSP system verification, and briefly presents the design of PLL IP core in future work.
引文
1. Floy M.Gardner. Phaselock Technique(Second Edition)[M].New York. John Wiley, 1979.
2. Roland E.Best. Phase-Locked Loops Design, Simulation, and Application[M].北京:清华大学出版社, 2003.
3. Jim Dunning, Gerald Garcia, Jim Lundberg et al. An all-digital phase-locked loop with 50 cycle lock time suitable for high-performance microprocessors[J]. IEEE journal of Solid-State Circuits, 1995, 30(4): 412-422.
4. Ching-Che Chung, Chen-Yi Lee. An all-digital phase-locked loop for high-speed clock genetation. IEEE journal of Solid-State Circuits, 2003, 38(2): 347-351.
5.林旭,余锋.一种用于高速同步数据采集设备的数字锁相环[J].微电子学, 2003, 33(4): 348-351.
6.远坂俊昭著.锁相环(PLL)电路设计与应用[M].何希才译.北京:科学出版社, 2004.
7. Frank Herzel, Behzad Razavi. A study of oscillator jitter due to supply and substrate noise[J] IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46(1): 56-62.
8. Lee Chang-Hyeon, Jack Comish, Kelly McClellan et al. Design of low jitter PLL for clock generator with supply noise insensitive VCO[J]. IEEE journal of Solid-State Circuits, 1998, 1(31): 233-236.
9.蒋召宇. CMOS锁相环时钟发生器的设计与研究[D]:[硕士学位论文].合肥:合肥工业大学, 2004.
10. Mota Manuel, Christiansen Jorgen. A high-resolution time inter polator based on a delay locked loop and an RC delay line[J]. IEEE journal of Solid-State Circuit, 1993, 34(20): 1360-1366.
11. Lin Feng, Miller Jason, Schoenfeld Aaron, et al. A register-controlled symmetrical DLL for double-date-rate DRAM[J]. IEEE journal of Solid-State Circuit, 1999, 34(4): 565-568.
12. Eckerbert Daniel, Svensson Lars J, Larrsson-Edefors Per. A mixed-mode delay-locked loop architecture[C]. In: Proc IEEE Int Conf Comput Des VLSI Comput Process. Piscataway: Institute of Electrical and Electronics Engineers Inc., 2003, 261-263.
13. Saeki Takanori, Minami Koichiro, Yoshida Hiroshi, et al. A direct-skew-detect synchronous mirror delay for aplication-specific integrated circuits[J]. IEEE journal of Solid-State Circuit, 1999, 34(3): 372-379.
14. Dan H. Wolaver. Phase-Locked Loop Circuit Design[M]. London: Prentice Hall, 1991.
15. Hein J.P, Scot J.W.. Z-domain model for discrete-time PLL’s[J]. IEEE Transactions OnCircuit and Systems, 1988, 35(11): 1393-1400.
16. F.M.Gardner. Charge-Pump Phase-Locked Loops[J]. IEEE Transactions on Communication, 1980, 28(11): 1894-1898.
17. Razavi Behzad. Design of Analog CMOS Integrated Circuits[M]. New York: McGraw-Hill, 2001.
18. Phillip E.Allen, Douglas R.Holberg. CMOS Analog Circuit Design(Second Edition)[M]. London: Ocford University Press, 2002.
19. David A.Johns, Ken Martin.模拟集成电路设计[M].曾朝阳,赵阳,方顺等译.北京:机械工业出版社, 2005. 465-493.
20. Y.Fouzar, M.Sawan, Y.Savaria, Very short locking time PLL based on controlled gain technique[C]. In: The 7th IEEE International Conference on Electronics, Circuits and Systems, 2000, 252-255.
21. Bergmans J.W.M.. Effect of loop delay stability of discrete-time PLL[J]. IEEE Transactions on Circuits and Systems, 1995, 42(4): 229-231.
22.姜梅,刘三清,李乃平等.用于电荷泵锁相环的无源滤波器的设计[J].微电子学, 2003, 33(4): 339-343.
23. Seiichi Saito, Tetsuro Kato, Shuichi Nitta. PLL noise reduction circuit to stabilize the disturbed clock pulse due to noise[C]. In: IEEE International Symposium on Electromaqnetic Compatibility, 1998, 1004-1009.
24. Xinhua He, Weixin Kong, Robert Newcomb, et al. Design and modelling of a low phase noise pll frequency synthesizer[C]. In: 06. 8th International Conference on Solid-State and Integrated Circuit Technology, 2006, 1571-1573.
25.屈强,曾烈光.一种用于高速锁相环的零死区鉴频鉴相器[J].电子设计, 2006, 22(12-2): 235-237.
26. K.Arshak, O.Abubaker, E.Jafer. Design and simulation difference types CMOS phase frequency detector for high speed and low jitter PLL[C]. In: Proceedings of the Fifth IEEE International Caracas Conference on Device, Circuit and Systems, 2004, 188-191.
27.曾建平,谢海情,邹伟华等.低相位噪声、宽带宽、高频率数字鉴频鉴相器设计[J].宇航计测技术, 2005, 25(6): 44-49.
28.王晓娟. CMOS集成电荷泵锁相环的设计与研究[D]:[硕士学位论文].合肥:合肥工业大学, 2007.
29. Kyung-Soo Ha, Lee-Sup Kim. Charge-pump reducing current mismatching in DLLs and PLLs[C]. In: 2006 IEEE International Symposium on Circuits and Systems, 2006, 2221-2224.
30.胡锦,龙晖,易锋.一种高电流匹配精度电荷泵电路设计[J].宇航计测技术, 2007, 27(2): 45-49.
31. Christl Lauterbach, Werner Weber. Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps[J]. IEEE journal of Solid-State Circuits, 2000, 35(5): 719-723.
32. Khalil Arshak, Omar Abubaker, Essa Jafer. Improved charge pump for reduced clock feed through and charge sharing suppression[C]. In: Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004, 192-194.
33. Z.Chen, F.Blaabjerg, J.K.Pedersen. A study of parallel operations of active and passive filters[C]. In: 2002 IEEE 33rd Annual Power Electronics Specialists Conference, 2002, 1021-1026.
34. Xu Donglin, Ren Junyan. Study of parasitic capacitance effect on low pass CMOS active filters[C]. In: Proceedings 5th International Conference on ASIC, 2003, 21-24.
35. Alan Hastings.模拟电路版图的艺术第二版(英文版)[M].北京:电子工业出版社,2006.
36. Alvaerz J, Sanchez H, Gerosa G. A wide-bandwidth low-voltage PLL for PowerPC microprocessors[J]. IEEE JSSC, 1995, 30(4): 383-390.
37. Chen W Z, Chang J X, Hong Y J, et al. A 2v 2.3/4.6GHz dual-band frequency synthesizer in 0.35um digital CMOS process[J]. IEEE journal of Solid-State Circuits, 2004, 39(1): 234-237.
38. Kaushik Sengupta, T.K.Bhattacharyya, Hossein Hashemi. A nonlinear transient analysis of regenerative frequency dividers[J]. IEEE Transactions on Circuits and Systems, 2007, 54(12): 2646-2660.
39. Zvi Nativ. The application of a frequency multiplier design method to the design of microwave parametric dividers[J]. IEEE Transaction on Microwave Theory and Techniques, 1987, 35(2): 189-194.
40. Chi-Hsueh Wang, Chung-Chun Chen, Ming-Fong Lei, et al. A 66-72 GHz divide-by-3 injection-locked frequency divider in 0.13um CMOS technology[C]. In: IEEE Asian Solid-State Circuits Conference, 2007, 344-347.
41. Dan Clein著. CMOS集成电路版图概念、方法与工具[M].邓红辉,王晓蕾,耿罗锋等译.北京:电子工业出版社, 2006.
42.贝斯克. Verilog HDL硬件描述语言[M].第2版.徐振林等译.北京:机械工业出版社, 2000, 1-5.
