摘要
随着半导体工艺技术的不断进步，金属氧化物半导体场效应晶体管(MOSFET)的特征尺寸也在不断的减小。当传统的SiO_2栅介质层厚度减小到几个原子尺度大小时，由于量子隧穿效应的影响，SiO_2将失去介电特性，使MOS器件的栅极漏电和静态功耗急剧的增加。为此，采用高介电常数（高k）栅介质取代SiO_2成为了必然趋势。然而，当高k栅介质的物理厚度变得可以和器件的沟道长度相比拟时，除了短沟道效应(SCE)、漏致势垒降低效应(DIBL)外，边缘场效应对MOSFET阈值电压的影响也越来越严重。针对这些现象，本文主要在理论和实验两个方面对高k栅介质MOSFET的特性和高k栅介质材料的制备进行了研究。在理论方面，研究了高k栅介质对于MOS器件的影响，建立起考虑这些效应的阈值电压模型。在实验方面，采用原子层淀积(ALD)技术生长高k栅介质薄膜，并对其物理和电学特性做了详细的分析。
首先，本文对高k栅介质纳米尺度MOS器件的特性进行了研究。随着MOSFET特征尺寸的不断减小，不断涌现出一些新的物理现象（如：栅极漏电增加、SCE等）弱化MOS器件的性能。同时，为了减小栅漏电流而使用的高k栅介质由于其较大的物理厚度引入了一种边缘感应势垒降低(FIBL)效应，增加器件的关态漏电流，极大地退化了器件的关态特性。本文提出一种等效耦合电容理论，可以很好地解释FIBL效应背后的物理机制，帮助更好地理解这种高k栅介质引入的边缘效应。通过优化器件结构（采用低介电常数材料作为侧墙介质、较短的侧墙长度、较低的结深和较短的栅/LDD交叠区长度等）可以很好的抑制FIBL效应，改善器件的关态特性。同时利用提出的等效耦合电容理论，研究了叠栅结构对于FIBL效应的抑制作用，发现采用低介电常数材料作为底层材料时，对于FIBL效果的抑制作用更好。和其他关于FIBL效应的研究相同，漏极关态电流被来表征FIBL效应对于器件关态特性的影响。但是，在一些特殊的情况下，这种方法会出现一些很难解释的现象。于是，本文又提出了一种新的研究关态漏电流的方法。通过把关态漏电流分为源漏电流、衬底漏电流和栅漏电流三部分，分别研究了高k栅介质以及漏端电压对于各关态漏电流组成部分的影响。结果表明，对于实际应用中的高k栅介质纳米MOSFET来说，以亚阈值漏电流为主体的源极漏电流成为了关态漏电流的主要组成部分。相比较传统的单以漏端关态电流作为表征关态漏电的方法，本文提出的方法可以更好帮助研究和理解纳米高k栅MOSFET的关态漏电流特性。
归根结底，高k栅介质MOSFET关态漏电流的变化主要是因为阈值电压波动引起的，所以对于高k栅介质MOSFET阈值电压的研究也尤为重要。本文考虑LDD区较低的内建电势以及LDD区的压降，通过解二维泊松方程，得到一种高k栅MOSFET阈值电压模型。基于这个模型，分别研究了FIBL效应和DIBL效应对于阈值电压的影响。通过比较LDD MOSFET和非LDD MOSFET的阈值电压漂移量发现，LDD MOSFET的阈值电压受沟道长度、漏端电压以及栅介电常数的影响较小。相比较非LDD MOSFET，LDD MOSFET拥有着较强的抵抗FIBL效应和SCE的能力。同时，为了解决多晶硅栅耗尽等问题，金属栅的引入需要对金属栅/高k栅介质MOSFET的阈值电压进行建模研究。本文研究了金属栅/高k栅介质/SiO_2/Si交叠结构对于阈值电压的影响，考虑金属栅极功函数的漂移以交叠结构对于平带电压的影响，通过边界条件求解二维表面势分布的泊松方程方程，得到金属栅/高k栅介质/SiO_2/Si交叠结构MOSFET的阈值电压模型。然后主要对阈值电压的模型进行了分析和讨论。这两个阈值电压模型都通过数值仿真验证，验证结果表明理论模型计算结果和模拟结果二者吻合良好。
实验方面，为了解决HfO_2材料的热稳定问题，采用原子层淀积(ALD)设备，通过交叠生长HfO_2和Al_2O_3的方式制备了HfAlO高k栅介质薄膜，并研究了HfAlO薄膜的物理和电学性质。我们分析了采用TMA+H_2O和TEMAH+H_2O生长HfAlO薄膜的原理，得到了四个半反应，并根据这四个半反应得到HfAlO薄膜生长中的重复单元Al-O-Hf-O (Hf-O-Al-O)，这种新的键合方式使得淀积的薄膜集成了HfO_2和Al_2O_3的优点，并且薄膜的特性也随着Hf和Al的不同组分变化。然而，随着单个重复单元中Hf和Al脉冲数目的增加，HfAlO薄膜的特性越来越趋近于HfO_2和Al_2O_3简单的叠加。除了使用H_2O以外，我们还使用了O_3作为氧化剂制备了HfAlO栅介质薄膜，从分析中可以看出使用O_3作为氧化剂生长的HfAlO薄膜，其组成结构和键合方式与使用H_2O生长的HfAlO薄膜相同。但由于O_3的强氧化性，所生长的HfAlO薄膜在电特性方面和采用H_2O生长的薄膜有了一定区别，具体表现在C-V曲线的漂移和低介电常数界面层的生长，而后者直接导致所生长栅介质薄膜介电常数的降低，但是热退火的使用在一定程度上会改善HfAlO栅介质薄膜的特性。
With the continuous development of semiconductor technology, the feature size ofthe metal-oxide-semiconductor field-effect transistor (MOSFET) is also continuouslyscaling down. However, gate leakage current and static power consumption increasedramatically due to quantum tunneling effect as the thickness of conventional SiO_2gatedielectric is reduced to the level of several atomic layers. To overcome these problems,the use of the high dielectric constant (high-k) gate dielectric to replace SiO_2hasbecome an inevitable trend. However, when the physical thickness of the high-k gatedielectric becomes comparable to the channel length of the device, influence of thefringing-induced barrier lowering (FIBL) effect on the threshold voltage becomes moreand more serious besides short-channel effect (SCE) and drain-induced barrier lowering(DIBL) effect. Aiming at the above problems, theoretical and experiment workinvolving the characteristics of MOSFET with high-k gate dielectric and preparation ofhigh-k gate dielectric materials is respectively performed to find relevant solutions inthis thesis. Theoretically, the influences of high-k gate dielectric on the characteristics ofMOSFET are studied, and threshold voltage model is established by considering theseparasitic effects. Experimentally, atomic layer deposition (ALD) technology is used todeposit high-k gate dielectric materials, and the physical and electrical properties ofthese materials are analyzed in detail.
The characteristics of nano-scale MOSFET with high-k gate dielectric areinvestigated. With the aggressive reduction of feature size of MOSFET, some physicalphenomena (such as: gate leakage current, SCE, etc.) continuously occur to weaken theperformance of MOSFET. Meanwhile, the use of high-k gate dielectric introduces anfringing-induced barrier lowering (FIBL) effect, which can greatly degrade the off-statecharacteristics of MOSFET. An equivalent coupling capacitance theory is presented tohelp understanding the FIBL effect, and can explain the physical mechanism behind theFIBL effect better. By optimizing the device structure (adopting low-k sidewallmaterials, shorter sidewall length, lower junction depth and shorter gate/LDDoverlapped region length, etc.), the FIBL effect can be well suppressed, and the off-satecharacteristics are improved. The FIBL effect can also be suppressed by using stackedgate structure, especially, when the underlying material using a low-k material. Similarto other studies on the FIBL effect, off-state leakage current is used to characterize theeffects of FIBL. However, in some special cases, there are some phenomenona which are difficult to explain by this method. Thus, a new research method of off-state leakagecurrent is presented. The total leakage current is divided into three parts: source leakagecurrent, substrate leakage current and gate leakage current. The influences of FIBLeffect and DIBL effect on each component are investigated respectively. The resultsshow that, for the practical application of nano-scale MOSFET with high-k gatedielectric, the source leakage current becomes a major component of the total leakagecurrent. The proposed method can help studying and understanding the off-statecharacteristics of nano-scale MOSFET with high-k gate dielectric.
Ultimately, the changes in the off-state leakage current of high-k MOSFET arecaused by threshold voltage fluctuations. So, it is particularly important to study thethreshold voltage behavior of high-k MOSFET. The study investigates the influence ofthe voltage drop across the lightly-doped-drain (LDD) region and the built-in potentialon MOSFET, a threshold voltage model for high-k gate dielectric MOSFET isdeveloped by solving the2D Poisson’s equation. The model can predict the FIBL effectand the SCE. Based on this model, the relationship between the threshold voltageroll-off and the channel length, drain voltage and the gate dielectric permittivity isinvestigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends thechannel length, the drain voltage and gate dielectric permittivity lightly. Meanwhile, inorder to solve the problem of poly-silicon gate depletion, the introduction of metal gateneeds to establish a new threshold voltage model for high-k/metal gate MOSFET. Thestudy investigates the influences of the metal-gate and high-k/SiO_2/Si stacked structureon MOSFET. The flat-band voltage is revised by considering the influences of stackedstructure and metal-semiconductor work function fluctuation. A threshold voltageanalytical model for metal-gate/high-k/SiO_2/Si stacked MOSFET is developed bysolving these Poisson’s equations using the boundary conditions. These two models areverified by numerical simulation, the results show that the theoretical model calculationresults and simulation results are in good agreement.
Experimentally, in order to improve the thermal stability of HfO_2gate dielectric,HfAlO thin film is deposited using atomic layer deposition (ALD) technology byalternating the growth of HfO_2and Al_2O_3. The physical characteristics and electricalproperties of the HfAlO film deposited on p-type (100) Si substrates are investigated.The growth principle of HfAlO using TMA+H_2O and TEMAH+H_2O is analyzed. Theformation of Al-O-Hf-O (Hf-O-Al-O) bond in the film is revealed to impact thecharacteristics of Hf-Al-O films. And the properties of the deposited film vary with thechanges in the proportion of Hf and Al. With the number of cycles pulsed of Al_2O_3and HfO_2in one bilayer, the influences of Al-O-Hf-O (Hf-O-Al-O) unit on thecharacteristics of the Hf-Al-O film are gradually weakened. The behavior of depositedfilm gradually becomes similar to that of a simple stack of HfO_2and Al_2O_3. In additionto H_2O, O_3is also used as the oxidant to deposite the HfAlO gate dielectric film. It canbe seen from the analysis results, there are no differences in the composition andbonding manner of the HfAlO thin film prepared by the O_3and the H_2O as oxidantrespectively. Due to the strong oxidizing nature of the O_3, an obvious shift of C-V curveis observed and a low dielectric constant interfacial layer is formed, leading to a smalldielectric constant of deposited HfAlO gate dielectric film. However, the annealingprocess can improve the electrical characteristics.
引文
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