摘要
单芯片计算机将传统PC机主板上的全部芯片最大限度地集成到单颗芯片中,使其重量、体积和功耗大幅下降,而性能却会得到很大改善。其中,系统总线的设计质量对缩小芯片面积,简化系统结构以及扩展外设都有非常积极的意义。本文围绕8086单芯片计算机开发项目开展研究工作,采用IP/SoC的设计方法,研究了8086 CPU与片上总线的接口方法,设计了8086单芯片计算机的系统总线IP,并实现了该IP在单芯片计算机验证平台上的集成与验证。
论文的主要工作和成果如下:
1.设计了面向8086 CPU的AHB系统总线IP;
2.设计了8086 CPU与AHB总线之间的接口;
3.完成了系统总线IP软核中的仲裁、译码和中断等模块的RTL级设计;
4.搭建了单芯片计算机的系统仿真平台,并在其上完成了系统总线IP软核的RTL级功能仿真;
5.搭建了单芯片计算机的FPGA原型,设计并完成了电子钟实验和VGA显示实验。
Computer-on-a-Chip (CoC) integrates ICs which distributed on the personal computer mainboard into one chip as many as possible , featuring better performance, lighter weight, smaller volume and lower power consumption. Integrating system bus into the CoC has lots of positive meaning for reducing chip area, simplifying system structure and expanding peripheral IPs. The research in this dissertation is based on the project of the 8086 Computer-on-a-Chip. Based on the IP/SoC design methodology, this dissertation studies the integration bwetten Chip-On-Board (COB) and On-Chip Bus ,designs system bus IP Core for CoC .Then, the integration and verification of this IP is performed on 8086 Computer-on-a-Chip platform.
The main works and achievements of this dissertation are as follows:
1. Developing an IP for the AHB Bus, which is working with 8086 CPU together;
2. Developing an interface between 8086 CPU and AHB Bus;
3. Completing the RTL-level design of several major functional modules, including Arbiter module, Interrupt module, and decoder module, etc;
4. Building an 8086 Computer-on-a-Chip simulation platform. Completing RTL-level simulation of this system bus IP Core by electronic clock and VGA experiments designed;
5. The whole system FPGA prototype verification is performed on the Altera DE2 evaluation board. The results show that this system bus IP is well designed and stable.
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