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在“
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”中,
命中:
2,064
条,耗时:小于0.01 秒
在所有数据库中总计命中:
4,963
条
1.
Custom
FPGA
processing for real-time fetal ECG extraction and identification
作者:
E. Torti
a
;
D. Koliopoulos
b
;
M. Matraxia
c
;
G. Danese
a
;
F. Leporati
a
;
leporati@unipv.it
关键词:
Embedded systems
;
Fetal ECG
;
Field programmable gate array (
FPGA
)
;
Biomedical instrumentation
刊名:Computers in Biology and Medicine
出版年:2017
2.
Emotional robot control architecture implementation using
FPGA
s
作者:
Carlos Dominguez
;
carlosd@disca.upv.es
Author Vitae
;
Houcine Hassan
husein@disca.upv.es
Author Vitae
;
Alfons Crespo
acrespo@disca.upv.es
Author Vitae
关键词:
Field-programmable gate array (
FPGA
)
;
Mobile robots applications
;
Embedded systems
;
Hardware/software co-design
;
VHDL
刊名:Journal of Systems Architecture
出版年:2017
3.
A spiking neural network for extraction of features in colour opponent visual pathways and
FPGA
implementation
作者:
Qi Yan Sun
a
;
b
;
sunqiyan99168@163.com
Author Vitae
;
Qing Xiang Wu
a
;
qxwu@fjnu.edu.cn
Author Vitae
;
Xuan Wang
a
Author Vitae
;
Lei Hou
a
Author Vitae
关键词:
Spiking neural network
;
Colour opponent
;
Visual pathways
;
Spike time dependent learning
;
FPGA
implementation
刊名:Neurocomputing
出版年:2017
4.
Configurable memristive logic block for memristive-based
FPGA
architectures
作者:
Patrick W.C. Ho
;
kecx2pha@nottingham.edu.my
;
Haider Abbas F. Almurib
;
T. Nandha Kumar
关键词:
FPGA
Architecture
;
Memristor
;
Logic block
;
Switch block
;
Configurable logic block
刊名:Integration, the VLSI Journal
出版年:2017
5.
Reconfigurable very high throughput low latency VLSI (
FPGA
) design architecture of CRC 32
作者:
Jubin Mitra
;
jm61288@gmail.com
;
jmitra@cern.ch
;
Tapan Nayak
nayak@cern.ch
关键词:
Big data application
;
High data rate
;
Error detection
;
Cyclic redundancy code (CRC)
;
Re-configurable architecture
;
FPGA
;
CRC-32
;
VLSI design
刊名:Integration, the VLSI Journal
出版年:2017
6.
Energy efficient parallel neuromorphic architectures with approximate arithmetic on
FPGA
作者:
Qian Wang
a
;
qwangku@tamu.edu
Author Vitae
;
Youjie Li
a
;
lyj2013apply@tamu.edu
Author Vitae
;
Botang Shao
b
;
jackieshao2011@gmail.com
Author Vitae
;
Siddhartha Dey
a
;
sidhart.de@email.tamu.edu
Author Vitae
;
Peng Li
a
;
pli@tamu.edu
Author Vitae
关键词:
Spiking neural network
;
Neuromorphic system
;
Approximate computing
;
Parallel architecture
刊名:Neurocomputing
出版年:2017
7.
A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array
作者:
Yonggang Wang
;
wangyg@ustc.edu.cn
;
Jie Kuang
;
Chong Liu
;
Qiang Cao
;
Deng Li
关键词:
Time-to-digital converter
;
Multiple channels
;
Time precision
;
Measurement dead time
;
Zynq-7000
FPGA
刊名:Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
出版年:2017
8.
Optimized thermal sensor allocation for field-programmable gate array temperature measurements based on self-heating test
作者:
Jingwei Li
;
Shiwei Feng
;
shwfeng@bjut.edu.cn
;
Yamin Zhang
;
Chao Wang
;
Xin He
关键词:
FPGA
;
Thermal sensors
;
Allocation optimization
;
Clustering
;
Self-heating test module
刊名:Microelectronics Journal
出版年:2017
9.
A spiking neural network for real-time Spanish vowel phonemes recognition
作者:
L. Miró
;
-Amarante
;
lmiro@us.es
Author Vitae
;
F. Gó
;
mez-Rodrí
;
guezAuthor Vitae
;
A. Jimé
;
nez-Ferná
;
ndezAuthor Vitae
;
G. Jimé
;
nez-MorenoAuthor Vitae
关键词:
Neuromorphic engineering
;
Address event representation (AER)
;
Event-based processing
;
FPGA
;
Digital cochlea
;
Speech recognition
刊名:Neurocomputing
出版年:2017
10.
A new area-efficient BCD-digit multiplier
作者:
Encarnació
;
n Castillo
a
;
encas@ugr.es
Author Vitae
;
Antonio Lloris
a
Author Vitae
;
Diego P. Morales
a
Author Vitae
;
Luis Parrilla
a
Author Vitae
;
Antonio Garcí
;
a
a
Author Vitae
;
Guillermo Botella
b
Author Vitae
关键词:
BCD enconding
;
Computer arithmetic
;
FPGA
;
IoT
;
Multiplier
刊名:Digital Signal Processing
出版年:2017
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